PID (proportional-integral-derivative) controllers are widely used for controlling voltage regulators. Many types of voltage regulators have an output filter response set by an actual or equivalent effective output inductance (L) and capacitance (C) of the system. Output capacitance and inductance variations can cause the voltage regulator system to become unstable, shutdown or malfunction. The double pole frequency of the output filter response, which is a function of output inductance and capacitance as given by 1/(2π√LC), is a key parameter in optimizing PID compensation for the control loop of a voltage regulator controller. If the actual output inductance and/or capacitance of a voltage regulator system varies from an expected or nominal value e.g. due to device variation, device aging, modular load applications, etc., the double pole frequency shifts as well. The initial optimized PID control loop, which is conventionally set based on a baseline (nominal) double pole frequency, often cannot compensate for variations in the actual double pole frequency, resulting in undesirable system behaviour.
For some voltage regulator system applications, the output inductance and capacitance can vary by up to +/−22%. Such LC variation means the double pole frequency can vary from −18% to 28%. For modular load applications, where the user can modify the regulator loading by plugging in additional loads and output capacitance, the capacitance and LC variation can be even larger. Conventional approaches for compensating against a wide range of variation in the double pole frequency include adding excessive amount of output capacitors, which increases system cost and requires excessive charging current during power up. Another conventional approach uses very conservative PID compensation, causing excessive overshoot or undershoot for systems with less capacitance or larger inductance than expected. Hence, there is a need for improved output filter response compensation techniques.